1. Field of the Invention
The present invention relates generally to fabrication methods of package structures, and more particularly, to a fabrication method of a package structure capable of increasing productivity and reducing fabrication costs.
2. Description of Related Art
In flip chip packaging technology, a semiconductor chip has a plurality of electrode pads formed on an active surface thereof, a substrate has a plurality of conductive pads formed on a surface thereof and corresponding in position to the electrode pads, and the electrode pads and the corresponding conductive pads are electrically connected by a plurality of solder bumps.
Compared with conventional wire bonding technology that establishes electrical connection between a semiconductor chip and a substrate through gold wires, flip chip packaging technology increases the circuit layout density, reduces the overall package size, decreases the impedance, and enhances the electrical performance of the package by dispensing with gold wires.
Conventionally, the fabrication method of a flip chip package structure comprises: providing a core board; forming sequentially on the core board a built-up structure with a plurality of bump pads and an insulating protective layer disposed therein with a plurality of openings for exposing the bump pads therefrom, followed by forming a surface treatment layer on the bump pads so as to form a full-panel packaging substrate; cutting the full-panel packaging substrate into a plurality of packaging substrate units or a plurality of strips, each of which comprises a plurality of packaging substrate units; and finally sending the packaging substrate units or strips to packaging factories for chip mounting, packaging and/or singulation.
If the full-panel packaging substrate is cut into a plurality of packaging substrate units, the chip mounting and packaging processes can only be performed on a single substrate unit at a time, thereby reducing productivity and increasing costs. Where the full-panel packaging substrate is cut into a plurality of substrate strips, and the frame of the substrate strips occupies a large effective area, thereby resulting in an increase in costs and a waste of materials. Furthermore, with packaging substrates becoming thinner, it is increasingly difficult to perform chip mounting or packaging on a substrate unit or strip.
On the other hand, if the chip mounting, packaging and singulation processes are directly performed on a full-panel packaging substrate, large-scale machines must be used, thereby increasing the equipment cost. Furthermore, alignment of a large-area packaging substrate is seldom accurate to thereby cause great errors in finally formed packaging substrate units, thus adversely affecting the product yield.
Therefore, it is imperative to overcome the above drawbacks of the prior art.